Capacitor structure having hemispherical grains

ABSTRACT

A first insulating layer is formed on semiconductor substrate, and a trench is formed in the first insulating layer. An amorphous silicon layer doped with impurities is formed on a side and bottom walls of the trench. Next, a resist material is partially filled in the trench so that an upper portion of the amorphous silicon layer is exposed. The exposed portion is implanted with impurity ions. After removal of the resist material, the amorphous silicon layer is heat treated so as to grow hemispherical grains on its surface.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor memory and a method offabricating the same, and more particularly, to a capacitor of asemiconductor memory device having a hemispherical grained (HSG) layerand a method of fabricating the same.

2. Description of Related Art

A conventional forming method of a semiconductor memory device isexplained in the following manner. A trench 2 is formed in a siliconsubstrate 1 and this trench is filled with a CVD oxide. The trench 2 isplanarized by chemical mechanical polishing (CMP) technique, so that atrench isolation region 2 is formed (see FIG. 1A).

Thereafter, a layer of thin oxide 3 is grown on all the surfaces bythermal oxidation. Layers of polycrystalline silicon 4 and tungsten 5are next deposited by CVD, and etched in order to define gate electrodes6 of MOS transistors and interconnects 7 (see FIG. 1B).

Next, a layer of interoxide 8 is deposited by CVD, and etched to definea bitline contact hole 9 in the layer of interoxide 8. Layers ofpolysilicon 10 and tungsten silicide are deposited on all the surfaces,and etched to form a bitline 12 (see FIG. 1C).

Moreover, layers of interoxide 13 silicon nitride 14 are respectivelydeposited by CVD. Cell contact holes 15 are defined both in layersinteroxide 13 and silicon nitride 14 by etching. A layer ofpolycrystalline silicon 16 heavily doped impurities is deposited on allthe surfaces, and is polished by CMP method. Only the contact holes 15are filled with the polycrystalline silicon 16 (see FIG. 2A).

A layer of a thick insulator 17 is deposited by CVD, and holes areopened in the insulator 17 by etching to form lower electrodes. A layerof a amorphous silicon 18, which is doped phosphorous of 0.5E20 to 3E20cm−3, is deposited by CVD, and only the opening holes are filled withresists 19 (see FIG. 2B).

Next, after all the surfaces are etched, the insulators 17 are removedby hydrogen fluoride solution, resulting that cylindrical lowerelectrodes 20 are formed (see FIG. 2C).

Heat treatment is carried out in a silane gas ambient under lowpressure, and hemispherical grains (HSGs) are grown on the surface ofthe amorphous silicon 18, so that lower electrodes 20 of cylindricalcapacitors have rough surfaces (see FIG. 3A).

A layer of thin silicon nitride 21 is deposited on the lower electrodes20 by CVD, and a layer of polycrystalline silicon doped impurities isdeposited on the silicon nitride 21. As a result, a memory cell, whichis composed of a cylindrical capacitor over the MOS transistors 3, havebeen completed (see FIG. 3B).

However, in the above-described conventional capacitor structure, thereare some problems, as is described below. Stress is caused on a lowerelectrode surface of a cylindrical capacitor because of a nucleation ofa polycrystalline silicon HSG, when a HSG rough surface is formed. Thestress is centralized on the top of the cylindrical capacitor, where thegrain of HSG closes together. It results that the grains on the top onthe lower electrode of the capacitor are peel off and cause a shortfailure between neighboring capacitors.

SUMMARY OF THE INVENTION

In order to solve these problems, the present invention is provided,wherein a semiconductor memory device, which has a capacitor comprisingof both the first electrode located outside of the capacitor and next tothe neighboring capacitor and having grain silicon grown from amorphoussilicon layer, and the second electrode formed on a semiconductorsubstrate, in which grain size at the top portion of the first electrodeis smaller than the other portions of the first electrode. Also, in thepresent invention, the impurity concentration at the top portion of theamorphous silicon is higher than the other portions.

According to the present invention, there is provided a method offabricating a semiconductor device, including forming a trench in theinterlayer of semiconductor substrate, depositing impurities doped aamorphous silicon served as a lower electrode all over the trench,forming a resist so as to expose the top portion of the amorphoussilicon in the trench, etching the amorphous silicon layer except forthe trench, implanting impurities into the top portion of the amorphoussilicon and growing HSG silicon by means of heat treatment after resiststrip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are sectional views for explaining a conventional methodfor forming a capacitor electrode.

FIGS. 2A to 2C are sectional views for explaining a conventional methodfor forming a capacitor electrode subsequent to FIG. 1C.

FIGS. 3A to 3C are sectional views for explaining a conventional methodfor forming a capacitor electrode subsequent to FIG. 2C.

FIGS. 4A to 4C are sectional views for explaining a method for forming acapacitor electrode according to the present invention.

FIG. 5 is a graph showing a failure chip dependent on phosphorousconcentration at the top of a lower electrode.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 4, after the same processes as the conventionalthrough FIG. 2B to FIG. 1 are performed, a layer of resist 102 is buriedinside a layer of amorphous silicon 101, and a upper portion of thelayer of the amorphous silicon 101 is exposed, as is shown in FIG. 4A.

Next, phosphorous ions are implanted at about 5 to 15 KeV. Also, arseniccan be implanted instead of phosphorous. The implantation is carried outonly at the top portion 104 of the amorphous silicon layer 101, becauseonly the top portion of the amorphous silicon layer 101 is exposed.

At this time, phosphorous ions of 0.5E20 to 3.0E20 cm−3 have alreadybeen doped the layer of the amorphous silicon 101, so that phosphorousconcentration of the top portion 104 of the amorphous silicon layer 101becomes higher than the other portions.

Thereafter, heat treatment is carried out in a silane gas ambient undervacuum condition as same as the conventional method, and grain size ofthe amorphous silicon layer 101 becomes larger. It results that thegrain grows into a hemispherical grain (HSG) and the lower electrode 105of the capacitor has a HSG rough surface.

Moreover, a cylindrical capacitor is formed by using the conventionalmethod.

In the present embodiment, the grain growth rate at the top portion ofthe lower electrode 104 is larger than at the other portions and it isdifficult to form HSG, because phosphorous concentration of the topportion is higher than the other portions.

FIG. 5 shows a result that a short failure between neighboringcylindrical capacitors is checked electrically. In FIG. 5, the graphshows failure chip versus phosphorous concentration of the top portion.The graph shows that the failure chip rapidly decrease with increase ofthe phosphorous concentration and saturates at the concentration ofabove 3E20 cm−3.

For example, when the amorphous silicon layer 101 has already been dopedphosphorous ions of 1 E20 cm−3, a net concentration is above 3E20 cm−3at the top portion if ion implantation is carried out at above 2E20 cm−3dose.

As described above in detail, in the manufacturing steps of the presentinvention, the top portion of a amorphous silicon layer is dopedphosphorous prior to a HSG growth of the amorphous silicon layer whichserves as a lower electrode, wherein the phosphorous concentration ofthe amorphous silicon layer becomes higher than the other portions. Itresults that HSG growth is suppressed at the top portion of theamorphous silicon layer. So that the HSG silicon of the top portion doesnot peel off and failures of electrical short do not occur even ifstress is caused during the HSG growth or in the step followed by theHSG growth. Therefore, it is possible to realize highly reliablecapacitor.

1. A capacitor of a memory cell formed on a silicon substrate, saidcapacitor comprising: a first electrode and second electrode, said firstelectrode disposing opposite to said second electrode and adjacent tothe neighboring capacitor; said first electrode having HSG roughnessgrown from amorphous silicon on its surface, the HSG roughness of thetop portion of said first electrode being smaller than the otherportions of said first electrode.
 2. The capacitor of the claim 1,wherein said first electrode disposes outside said capacitor and saidsecond electrode disposes inside said capacitor.
 3. The capacitor of theclaim 1, wherein said first electrode is made from amorphouse silicon.4. The capacitor of the claim 3, wherein impurity concentration at thetop portion of said first electrode is higher than that at the otherportion of said first electrode.
 5. The capacitor of the claim 4,wherein said impurity is either phosphorous or arsenic.
 6. The capacitorof the claim 4, wherein impurity concentration at the top portion ofsaid first electrode is more than eE20 cm⁻³. 7-10. (canceled)